The interior of the dielectrics dividing wafer is divided potentially or electrically into many semiconductor areas in order to avoid operational interference among semiconductor elements and circuit elements formed therein. Moreover, the devices are usually made with these circuit elements allotted to these semiconductor areas, regardless of whether they are of the bipolar type, MOS type or BiMOS type. A generally known means to make such a division is the bonding-dividing method. This method, however, does not completely prevent operational interference among the circuit elements because the semiconductor areas are separated from each other only potentially by a "pn" junction in a reverse condition. Moreover, unexpected trouble may occur during operations because of the effects of parasitic transistors. The circuit elements must therefore be separated from each other by more than a certain minimum amount.
The dielectrics dividing method electrically insulates the semiconductor areas from each other, providing insulating isolation rather than potential isolation, thereby allowing very little operational interference among the circuit elements, an provides the added benefit of making it possible to arrange the circuit elements more closely, which is necessary to ensure greater circuit integration. The dielectrics dividing wafer can therefore be used in high-performance circuits, as well as in high-frequency circuits, although it is more expensive than the bonded-divided wafer. The present invention is related to the production of a wafer by the dielectrics dividing method.
Dielectrics dividing wafer has been known for a long time as a wafer constructed with many semiconductors, consisting of monocrystalline silicon carried on a wafer substrate made of polycrystalline silicon via silicon oxide dielectric films or silicon nitride films or composite films made up of both compounds. A method to manufacture this type of wafer with dielectrics dividing construction in which the semiconductor areas are carried by the polycrystalline silicon may include, as disclosed in U.S. Pat. Nos. 3,534,234, 3,648,125 and 3,970,486, processes to trench V-shaped grooves in a frame-like pattern over one face of a monocrystalline silicon wafer, cover the face including the grooves with dielectric films, fill in the grooves with polycrystalline silicon deposited by the CVD process or some other means to make deposits with the desired thickness, and divide the monocrystalline silicon wafer into island-like semiconductor areas carried by the polycrystalline silicon via the dielectric films, by grinding the monocrystalline silicon wafer from the other side until the polycrystalline silicon in the grooves are exposed. A method to make the groove rectangular is disclosed in U.S. Pat. No. 3,966,577, and a method to fill these rectangular grooves with an insulating material is disclosed in U.S. Pat. No. 8,979,765.
The recent development of technology for bonding monocrystalline silicon substrates has achieved the stage of practical application, making it possible to produce dielectrics dividing wafers by combining technology for cutting trenches with the reactive-ion etching process. The bonding of substrates has been known for a long time having been disclosed in the Japanese laid-open patent application No. 39-17869, though it was not successful in practical application despite the fact that it drew much interest. However, the advancement of technologies to grind and clean surfaces to be bonded has made practical application possible.
With this method of dividing dielectrics of bonding substrates, two silicon substrates are bonded together with a silicon oxide film interposed between them, one of the substrates is ground to the desired thickness, small trenches are cut from the surface thereof in a frame pattern deeply enough to reach the silicon oxide film on the bonded surface, the surface including the trenches is covered with a dielectric film, and the trenches are filled with polycrystalline silicon, then the polycrystalline silicon and the dielectric film on the one side of the substrate is removed. Thus, the substrate is divided into several semiconductor areas in which one of the substrates is insulated by the silicon oxide film and the substrates are separated from each other by the dielectric film.
The dielectrics dividing wafer using polycrystalline silicon as its substrate entered the practical application phase quite some time ago, as did the one which applied a substrate bonding construction, and both are used in integrated circuit devices requiring small power. However, recent increasing applications to drive loads directly with integrated circuit devices have found the conventional dielectrics dividing wafers described above to be unsuitable when circuit elements such as vertical-type field effect transistors that can handle more power are incorporated in such devices.
The vertical circuit elements that will handle large power require disposing electrode films for internal wiring or external connection both on the surface of a wafer and on the rear side thereof. However, in conventional dielectrics dividing wafer constructions, a dielectric film exists between the semiconductor areas where the circuit elements are to be built in, and polysilicon or silicon substrates which are the base substance of the wafer. Thus, terminals cannot be led out for the vertical circuit elements from the rear of the wafer.
As a result, in convention processes, the thickness of the semiconductor area is initially increased and an embedded layer with a high concentration of impurity is disposed at the bottom thereof, whereas a connection is made to an electrode film on the surface via the connection layer with a high concentration of impurities. There is a limit, however, to the thickness of the semiconductor area, which makes it difficult to make vertical circuit elements with a sufficient power capacity, and requires additional processes and spaces to create the embedded and connection layers, thus offsetting the advantages of the dielectrics separation.
It is possible to utilize a wafer with the construction proposed by Proceeding IEEE 1987 Custom IC Conference, pp. 443-446, May 1987, since the dielectrics dividing wafer is advantageous for building vertical circuit elements that can solve the above problems. This wafer has a silicon substrate surface initially provided with a silicon oxide film with the desired pattern, upon which silicon can be grown epitaxially, while a continuous epitaxial layer is obtained on the monocrystalline silicon, and polycrystalline silicon forms on the silicon oxide film. For instance, the epitaxial layer is divided into more than two semiconductor areas insulated from the substrate by the silicon oxide film via cutting trenches in the polycrystalline silicon that reach the silicon oxide film and cover the trenches with dielectric film. As a result, vertical circuit elements that can handle large power can be built into each semiconductor area as well as into the silicon substrate that is connected to the semiconductor areas.
Such a construction, however, makes the multiple semiconductor areas linked to the silicon substrate common to them, thus resulting in imperfect dielectric separation, and tending to cause insufficient separation among the vertical circuit elements. In addition, although an integrated circuit device requires vertical circuit elements capable of handling large power, as well as horizontal circuit elements capable of handling small power be incorporated in the wafer surface in an ordinary planar structure, the above construction is very inconvenient for separating the wafer into two types of dielectrics, i.e., one a semiconductor area shallow on the surface and suitable for small circuit elements, and the other a semiconductor area that extends from the surface to the rear side and is suitable for vertical circuit elements.
In order to solve these conventional problems, it is a primary objective of the present invention to divide a wafer dielectrically into a semiconductor area which extends from the surface to the rear side, thereby making it suitable for building vertical circuit elements, and a further secondary objective is to divide a wafer surface dielectrically into a semiconductor area suitable for building circuit elements with a planar structure.